A 0.55 V 60 dB-DR Fourth-Order Analog Baseband Filter

被引:69
作者
De Matteis, Marcello [1 ]
D'Amico, Stefano [1 ]
Baschirotto, Andrea [2 ]
机构
[1] Univ Salento, Dept Innovat Engn, I-73100 Lecce, Italy
[2] Univ Milano Bicocca, Dept Phys G Occhialini, I-20126 Milan, Italy
关键词
Analog filters; CMOS; continuous time; low voltage; zero-IF receivers; LOW-VOLTAGE; DESIGN;
D O I
10.1109/JSSC.2009.2024801
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A 0.55 V supply voltage fourth-order low-pass continuous-time filter is presented. The low-voltage operating point is achieved by an improved bias circuit that uses different opamp input and output common-mode voltages. The fourth-order filter architecture is composed by two Active-G(m)-RC biquadratic cells, which use a single opamp per-cell with a unity-gain-bandwidth comparable to the filter cut-off frequency. The 3 dB filter frequency is 12 MHz and this is higher than any other low-voltage continuous-time filter cut-off frequency. The 3 dB frequency can be adjusted by means of a digitally-controlled capacitance array. In a standard 0.13 mu m CMOS technology with V-THN approximate to 0.25 V and V-THP approximate to 0.3 V, the filter operates with a supply voltage as low as 0.55 V. The filter (total area = 0.47 mm(2)) consumes 3.4 mW. A 8 dBm-in-band IIP3 and a 13.3 dBm-out-of-band IIP3 demonstrate the validity of the proposal.
引用
收藏
页码:2525 / 2534
页数:10
相关论文
共 22 条
[1]   A 1-V 1.8-MHz CMOS switched-opamp SC filter with rail-to-rail output swing [J].
Baschirotto, A ;
Castello, R .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1997, 32 (12) :1979-1986
[2]   The effect of technology scaling on power dissipation in analog circuits [J].
Bult, K .
ANALOG CIRCUIT DESIGN: RF CIRCUITS: WIDE BAND, FRONT-ENDS,DAC'S, DESIGN METHODOLOGY AND VERIFICATION FOR RF AND MIXED-SIGNAL SYSTEMS, LOW POWER AND LOW VOLTAGE, 2006, :251-294
[3]  
Chatterjee B, 2003, ISLPED'03: PROCEEDINGS OF THE 2003 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, P122
[4]   0.5-V analog circuit techniques and their application in OTA and filter design [J].
Chatterjee, S ;
Tsividis, Y ;
Kinget, P .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2005, 40 (12) :2373-2387
[5]  
CHATTERJEE S, 2005, IEEE ISSCC FEB 10, V1, P506
[6]   A 4th-order active-Gm-RC reconfigurable (UMTS/WLAN) filter [J].
D'Amico, Stefano ;
Giannini, Vito ;
Baschirotto, Andrea .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2006, 41 (07) :1630-1637
[7]   CIRCUIT ARCHITECTURES FOR HIGH LINEARITY MONOLITHIC CONTINUOUS-TIME FILTERING [J].
DURHAM, AM ;
HUGHES, JB ;
REDMANWHITE, W .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 1992, 39 (09) :651-657
[8]   A 100KS/s 65 dB DR Σ-Δ ADC with 0.65V supply voltage [J].
Gambini, Simone ;
Rabaey, Jan .
ESSCIRC 2007: PROCEEDINGS OF THE 33RD EUROPEAN SOLID-STATE CIRCUITS CONFERENCE, 2007, :202-205
[9]   A 2.7-V CMOS dual-mode baseband filter for PDC and WCDMA [J].
Hollman, T ;
Lindfors, S ;
Länsirinne, M ;
Jussila, J ;
Halonen, KAI .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2001, 36 (07) :1148-1153
[10]   Design of low-voltage CMOS continuous-time filter with on-chip automatic tuning [J].
Huang, HZ ;
Lee, EKF .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2001, 36 (08) :1168-1177