Exploration of GFP frame delineation architectures for network processing

被引：2

作者：

Toal, C ^{[1
]}

Sezer, S ^{[1
]}

机构：

[1] Queens Univ Belfast, Sch Elect & Elect Engn, Belfast, Antrim, North Ireland

来源：

IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS | 2004年

关键词：

frame delineation; GFP; network processing; SoC;

D O I：

10.1109/SOCC.2004.1362390

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents the design and study of circuit architectures for gigabit GFP frame delineation and explores the trade-offs between the data-path (parallelism) and the corresponding hardware cost. The study targets the development of a SoC platform for the design of next generation network processing. Circuits with an 8-bit, 16-bit, 32-bit and a 64-bit data-path have been implemented and analysed in terms of, scalability, hardware cost, speed, and data throughput capabilities. The circuit analysis is based on performance results with the UMC 0.18 mum standard cell libraries obtained using Synopsys physical compiler. Analysis shows that the 64-bit data-path architecture is able to achieve data rates beyond 10Gbps whereas the 8-bit data-path architecture is very compact and operates with a clock rate of close to 300MHz. Considering the throughput-rate versus silicon area cost as a measure of silicon area efficiency, then the 16-bit data-path architecture proves to be the most efficient.

引用

页码：159 / 162

页数：4

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