A 0.7-V 870-μW Digital-Audio CMOS Sigma-Delta Modulator

被引：87

作者：

Park, Hyunsik ^{[1
]}

Nam, KiYoung ^{[1
]}

Su, David K. ^{[1
]}

Vleugels, Katelijn ^{[1
]}

Wooley, Bruce A. ^{[1
]}

机构：

[1] Stanford Univ, Ctr Integrated Syst, Stanford, CA 94305 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2009年 / 44卷 / 04期

关键词：

Analog-to-digital conversion; chopper stabilization; CMOS analog integrated circuits; digital audio; input feed-forward; low-voltage low-power analog circuits; oversampling A/D converters; sigma-delta modulation; switched-capacitor circuits; ADC;

D O I：

10.1109/JSSC.2009.2014708

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper introduces a power-efficient, chopper-stabilized switched-capacitor sigma-delta (EA) modulator that combines delayed input feedforward and single-comparator tracking multi-bit quantization to achieve high-precision, low-voltage analog-to-digital (AID) conversion. An experimental prototype of the proposed architecture has been integrated in a 0.18-mu m CMOS technology. The prototype operates from a 0.7-V supply voltage with a sampling rate of 5 MSamples/sec and consumes only 870 mu W of total power. The converter achieves a dynamic range of 100 dB, a peak signal-to-noise ratio (SNR) of 100 dB and a peak signal-to-noise and distortion ratio (SNDR) of 95 dB for a 25-kHz signal bandwidth.

引用

页码：1078 / 1088

页数：11

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