Fault Simulation for Analog Test Coverage

被引:0
作者
Sequeira, Jyotsna [1 ]
Natarajan, Suriyaprakash [1 ]
Goteti, Prashant [1 ]
Chaudhary, Nitin [1 ]
机构
[1] Intel Corp, Santa Clara, CA 95051 USA
来源
PROCEEDINGS 2016 IEEE INTERNATIONAL TEST CONFERENCE (ITC) | 2016年
关键词
TEST METRICS;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A practical fault simulation methodology for analog circuits in mixed-signal designs is presented. The methodology leverages the mixed-signal simulation environment of a product and performs mixed-signal fault simulation of embedded analog circuits. A set of open-circuit and short-circuit faults are extracted with guidance from layout parasitics, and automatically injected in to the netlist. Fault coverage of manufacturing tests on faults in the transmitter of a high speed serial interface design are reported with two different observation criteria. Results indicate the amount of test reduction that can be achieved and the importance of appropriate observation in fault detection.
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页数:7
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