A 160 GHz Pulsed Radar Transceiver in 65 nm CMOS

被引:59
作者
Ginsburg, Brian P. [1 ]
Ramaswamy, Srinath M. [1 ]
Rentala, Vijay [1 ]
Seok, Eunyoung [1 ]
Sankaran, Swaminathan [1 ]
Haroun, Baher [1 ]
机构
[1] Texas Instruments Inc, Kilby Labs, Dallas, TX 75243 USA
关键词
CMOS; input compression point; mixer; mm-wave; noise figure; phased array; radar; wireless; IN-PACKAGE; POWER-AMPLIFIER; P-SAT; ARRAY; TRANSMITTER; DESIGN;
D O I
10.1109/JSSC.2014.2298033
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents a 160 GHz center frequency pulsed 65 nm CMOS transceiver for short range radar applications. Four phased array transceivers were implemented in a single chip with antennas implemented in a BGA package. The implemented transmitter is capable of producing pulses of 100 ps widths (>20 GHz RF bandwidth) at a 160 GHz carrier frequency. The measured effective isotropic radiated power ( EIRP) is 18.8 dBm for continuous wave outputs. The analog beam forming receiver achieves an overall gain of 42.5 dB, -14 dBm, IP1db, 7 GHz bandwidth, and a noise figure of 22.5 dB. The sliding window time-dilation baseband relaxes the output data rate and subsequent digital processing requirements. Fine grained duty cycling reduces power dissipation. The entire chip consumes 2.2W from 1.2/1.4 V supplies in a 65 nm digital CMOS process.
引用
收藏
页码:984 / 995
页数:12
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