First Demonstration of 3D SRAM Through 3D Monolithic Integration of InGaAs n-FinFETs on FDSOI Si CMOS with Inter-layer Contacts

被引：0

作者：

Deshpande, V. ^{[1
]}

Hahn, H. ^{[1
]}

O'Connor, E. ^{[1
]}

Baumgartner, Y. ^{[1
]}

Sousa, M. ^{[1
]}

Caimi, D. ^{[1
]}

Boutry, H. ^{[2
]}

Widiez, J. ^{[2
]}

Brevard, L. ^{[2
]}

Le Royer, C. ^{[2
]}

Vinet, M. ^{[2
]}

Fompeyrine, J. ^{[1
]}

Czornomaz, L. ^{[1
]}

机构：

[1] IBM Res GmbH Zurich Lab, Saumerstr 4, CH-8803 Ruschlikon, Switzerland

[2] CEA, Leti, MINATEC Campus,17 Rue Martyrs, F-38054 Grenoble 9, France

来源：

2017 SYMPOSIUM ON VLSI TECHNOLOGY | 2017年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We demonstrate, for the first time, the 3D Monolithic (3DM) integration of In0.53GaAs nFETs on FDSOI Si CMOS featuring short-channel Replacement Metal Gate (RMG) InGaAs n-FinFETs on the top layer and Gate-First Si CMOS on the bottom layer with TiN/W inter-layer contacts. State-of-the-art device integration is achieved with the top layer InGaAs utilizing raised source drain (RSD) and the bottom layer CMOS having Si RSD for nFETs, SiGe RSD for pFETs, implants, silicide and TiN/W plug contacts. The top layer InGaAs n-FinFETs are scaled down to L-g =25 nm and both the Si nFETs and pFETs in the bottom layer are scaled down to L-g similar to 15 nm. Finally, utilizing the inter-layer contacts, we demonstrate a densely integrated 3D 6T-SRAM circuit with InGaAs nFETs stacked on top of Si pFETs showing considerable area reduction with respect to a 2D layout.

引用

页码：T74 / T75

页数：2

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