A 1 V 23 GHz Low-Noise Amplifier in 45 nm Planar Bulk-CMOS Technology With High-Q Above-IC Inductors

被引：11

作者：

Wang, Wen-Chieh ^{[1
]}

Huang, Zue-Der ^{[1
]}

Carchon, Geert ^{[2
]}

Mercha, Abdelkarim ^{[2
]}

Decoutere, Stefaan ^{[2
]}

De Raedt, Walter ^{[2
]}

Wu, Chung-Yu ^{[1
]}

机构：

[1] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu 300, Taiwan

[2] IMEC, B-3001 Louvain, Belgium

来源：

IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS | 2009年 / 19卷 / 05期

关键词：

CMOS; electrostatic discharge (ESD) protection; 45; nm; K; -band; low-noise amplifier (LNA);

D O I：

10.1109/LMWC.2009.2017611

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 23 GHz electrostatic discharge-protected low-noise amplifier (LNA) has been designed and implemented by 45 nm planar bulk-CMOS technology with high-Q above-IC inductors. In the designed LNA, the structure of a one-stage cascode amplifier with source inductive degeneration is used. All high-Q above-IC inductors have been implemented by thin-film wafer-level packaging technology. The fabricated LNA has a good linearity where the input I dB compression point (IP-1 (dB))is - 9.5 dBm and the input referred third-order intercept point (P-IIP3) is +2.25 dBm. It is-operated with a I V power supply drawing a current of only 3.6 mA. The fabricated LNA has demonstrated a 4 dB noise figure and a 7.1 dB gain at the peak gain frequency of 23 GHz, and it has the highest figure-of-merit. The experimental results have proved the suitability of 45 nm gate length bulk-CMOS devices for PF ICs above 20 GHz.

引用

页码：326 / 328

页数：3

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