VHDL-AMS model of a 40M/S 12 bits pipeline ADC

In this paper we describe the structure and the VHDL-AMS high level model of a 40MSample/S12 bit pipeline ADC. Design of high performance mixed signal circuits, like analog to digital converters require extensive simulations at different levels of analog design hierarchy. As we go deeper in details, down in, the analog hierarchy, these simulations become more and more CPU time expensive and so, the verification stage previous to manufacturing of a typical ADC design cycle requires enormous amounts of time. The use of high level models in the design of complex mixed signal circuits allows the exploration of different solutions with high enough accuracy and fast simulations. Performance of the model developed in this paper is compared with postlayout extraction simulations of the ADC. Utility of VHDL-AMS behavioural model is demonstrated with the calculation of ADC performance subject to some design parameters variation. http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=1706641