A Latchup-Free ESD Power Clamp Circuit with Stacked-Bipolar Devices for High-Voltage Integrated Circuits

被引：0

作者：

Park, Jae-Young ^{[1
]}

Song, Jong-Kyu ^{[1
]}

Jang, Chang-Soo ^{[1
]}

Kim, San-Hong ^{[1
]}

Jung, Won-Young ^{[1
]}

Kim, Taek-Soo ^{[1
]}

机构：

[1] Dongbu HiTek, TE Ctr, DE Team, Bucheon Si, Gyeonggi Do, South Korea

来源：

IEICE TRANSACTIONS ON ELECTRONICS | 2009年 / E92C卷 / 05期

关键词：

ESD (electrostatic discharge) ESD power clamp circuit; latch-up; stacked-bipolar devices; DESIGN; IMPACT;

D O I：

10.1587/transele.E92.C.671

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The holding voltage of high-voltage devices under the snapback breakdown condition has been known to be much smaller than the power supply voltage. Such characteristics cause high-voltage ICs to be susceptible to the transient latch-up failure in the practical system applications, especially when these devices are used as the ESD power clamp circuit. A new latchup-free design of the ESD power clamp circuit with stacked-bipolar devices is proposed and successfully verified in a 0.35 mu m BCD (Bipolar-CMOS-DMOS) process to achieve the desired ESD level. The total holding voltage of the stacked-bipolar devices in the snapback breakdown condition can be larger than the power supply voltage.

引用

页码：671 / 675

页数：5

共 50 条

[11] Bipolar ESD Power Clamp in High Voltage CMOS Based on TCAD Device Simulation
Betak, Petr
2009 32ND INTERNATIONAL SPRING SEMINAR ON ELECTRONICS TECHNOLOGY, 2009, : 513 - 515
[12] Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product
Lin, IC
Huang, CY
Chao, CJ
Ker, MD
Chuan, SY
Leu, LY
Chiu, FC
Tseng, JC
PROCEEDINGS OF THE 9TH INTERNATIONAL SYMPOSIUM ON THE PHYSICAL & FAILURE ANALYSIS OF INTEGRATED CIRCUITS, 2002, : 75 - 79
[13] Analysis and Solution to Overcome EOS Failure Induced by Latchup Test in A High-Voltage Integrated Circuits
Tsai, Hui-Wen
Ker, Ming-Dou
Liu, Yi-Sheng
Chuang, Ming-Nan
2013 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION, AND TEST (VLSI-DAT), 2013,
[14] Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product
Lin, IC
Huang, CY
Chao, CJ
Ker, MD
MICROELECTRONICS RELIABILITY, 2003, 43 (08) : 1295 - 1301
[15] Promise and Challenges of High-Voltage SiC Bipolar Power Devices
Kimoto, Tsunenobu
Yamada, Kyosuke
Niwa, Hiroki
Suda, Jun
ENERGIES, 2016, 9 (11)
[16] An Integrated Low-Power High-Voltage Driving Circuit for Digital Micromirror Devices (DMD™)
Wang, Jianbai
Huffman, James
Pinheiro, Paulo
Hall, James
2009 IEEE INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS, 2009, : 187 - 188
[17] State-of-the-art technologies and devices for high-voltage integrated circuits
Udrea, F.
IET CIRCUITS DEVICES & SYSTEMS, 2007, 1 (05) : 357 - 365
[18] Comparison Between High-Holding-Voltage SCR and Stacked Low-Voltage Devices for ESD Protection in High-Voltage Applications
Dai, Chia-Tsen
Ker, Ming-Dou
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2018, 65 (02) : 798 - 802
[19] Advances in devices and technologies for power and high voltage integrated circuits
Hardikar, S
De Souza, MM
Narayanan, EMS
PROCEEDINGS OF THE ELEVENTH INTERNATIONAL WORKSHOP ON THE PHYSICS OF SEMICONDUCTOR DEVICES, VOL 1 & 2, 2002, 4746 : 422 - 431
[20] An investigation on capacitance-trigger ESD protection devices for high voltage integrated circuits
Liang, Hailian
Nie, Weidong
Gu, Xiaofeng
Dong, Shurong
Lau, W. S.
MICROELECTRONICS RELIABILITY, 2014, 54 (6-7) : 1169 - 1172

← 1 2 3 4 5 →