A Latchup-Free ESD Power Clamp Circuit with Stacked-Bipolar Devices for High-Voltage Integrated Circuits

被引：0

作者：

Park, Jae-Young ^{[1
]}

Song, Jong-Kyu ^{[1
]}

Jang, Chang-Soo ^{[1
]}

Kim, San-Hong ^{[1
]}

Jung, Won-Young ^{[1
]}

Kim, Taek-Soo ^{[1
]}

机构：

[1] Dongbu HiTek, TE Ctr, DE Team, Bucheon Si, Gyeonggi Do, South Korea

来源：

IEICE TRANSACTIONS ON ELECTRONICS | 2009年 / E92C卷 / 05期

关键词：

ESD (electrostatic discharge) ESD power clamp circuit; latch-up; stacked-bipolar devices; DESIGN; IMPACT;

D O I：

10.1587/transele.E92.C.671

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The holding voltage of high-voltage devices under the snapback breakdown condition has been known to be much smaller than the power supply voltage. Such characteristics cause high-voltage ICs to be susceptible to the transient latch-up failure in the practical system applications, especially when these devices are used as the ESD power clamp circuit. A new latchup-free design of the ESD power clamp circuit with stacked-bipolar devices is proposed and successfully verified in a 0.35 mu m BCD (Bipolar-CMOS-DMOS) process to achieve the desired ESD level. The total holding voltage of the stacked-bipolar devices in the snapback breakdown condition can be larger than the power supply voltage.

引用

页码：671 / 675

页数：5

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