Continuous time sigma-delta modulator based on binary weighted charge balance

被引：3

作者：

Hernandez, L. ^{[1
]}

Pun, E. ^{[1
]}

Prefasi, E. ^{[1
]}

Paton, S. ^{[1
]}

机构：

[1] Univ Carlos III Madrid, Dept Elect Technol, Madrid 28911, Spain

来源：

ELECTRONICS LETTERS | 2009年 / 45卷 / 09期

关键词：

D O I：

10.1049/el.2009.0323

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A novel multibit continuous time sigma-delta modulator architecture that does not require a. ash converter is presented. The quantiser of this modulator is similar to an integrating ADC that is operated with a binary weighted charge balancing algorithm. The charge residue in the integrating ADC at the end of each conversion cycle is accumulated for the next conversion, providing first-order noise shaping. The modulator order can be increased by the addition of more integrating stages.

引用

页码：458 / 459

页数：2