Simulation of Charge-Trapping Effect on Floating Gate Si/Ge/Si Quantum Dots MOSFET Memory with High-κ Tunnel Oxide

In this paper, we report the simulation of floating gate MOSFET memory consists of Si/Ge/Si quantum dots for electronics storage nodes with high-kappa material as the tunnel oxide. Heterostructure quantum dot was proposed to maintain the good memory performance without losing the long retention characteristic. By replacing the SiO2 tunnel oxide with high-kappa material such as HfO2, ZrO2, and Y2O3 the leakage current due to the shrinkage of tunnel oxide thickness can be suppressed by the factor of 10 for the EOT lower than similar to 1nm. Here, the charge-trapping that generated by the defect at high-kappa material interface are fully considered. We found that the charge-trapping significantly affects the retention time and memory performance. By increasing the trapping depth and width, the memory operation performance markedly decline. Furthermore, as predicted, the retention time increase by taking accounts this charge-trapping.