Fast locking delay-locked loop using initial delay measurement

被引：4

作者：

Kim, T ^{[1
]}

Wang, SH ^{[1
]}

Kim, B ^{[1
]}

机构：

[1] Korea Adv Inst Sci & Technol, Dept Elect Engn & Comp Sci, Yusung Gu, South Korea

来源：

ELECTRONICS LETTERS | 2002年 / 38卷 / 17期

关键词：

D O I：

10.1049/el:20020626

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A delay-locked loop (DLL) architecture capable of incorporating fast locking and low jitter features simultaneously is reported. A test chip was fabricated in a 0.6 mum CMOS process to prove its functionality. The proposed DLL can align the internal clock to the external reference clock within two cycles and maintain its locking state with the aid of feedback operation.

引用

页码：950 / 951

页数：2

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