Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic

被引：12

作者：

Kim, Sunmean ^{[1
]}

Lee, Sung-Yun ^{[2
]}

Park, Sunghye ^{[2
]}

Kang, Seokhyeong ^{[2
]}

机构：

[1] Ulsan Natl Inst Sci & Technol, Dept Elect Engn, 50 UNIST Gil, Ulsan 44919, South Korea

[2] Pohang Univ Sci & Technol, Dept Elect Engn, 77 Cheongam Ro, Pohang 37673, Gyeongbuk, South Korea

来源：

2019 IEEE 49TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL) | 2019年

基金：

新加坡国家研究基金会;

关键词：

Multi-valued logic; Ternary logic circuits; Sequential logic circuits; Ternary clock signal; CNTFET;

D O I：

10.1109/ISMVL.2019.00015

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We propose a quad-edge-triggered flip-flop which captures and propagates a ternary data signal at four-edges of a ternary clock signal. The proposed circuit uses carbon nanotube FETs and consists of four types of logic gate: ternary clock driver, standard ternary inverter, binary inverter, and transmission gate. HSPICE simulation result has confirmed that power consumption of QETFF is lower than conventional single-edge-triggered flip-flop. The average power consumption is reduced by 31 % in flip-flop and 75 % in clock tree. We designed a ternary serial adder using QETFF and the energy efficiency of the proposed circuit is significantly improved compared to the previous design of ternary serial adder.

引用

页码：37 / 42

页数：6

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