Current-Mode Transceiver for Silicon Interposer Channel

被引：28

作者：

Lee, Seung-Hun ^{[1
]}

Lee, Seon-Kyoo ^{[2
]}

Kim, Byungsub ^{[1
]}

Park, Hong-June ^{[1
]}

Sim, Jae-Yoon ^{[1
]}

机构：

[1] Pohang Univ Sci & Technol POSTECH, Dept Elect Engn, Pohang 790784, Kyungbuk, South Korea

[2] Samsung Elect, Memory Div, Hwasung, South Korea

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2014年 / 49卷 / 09期

基金：

新加坡国家研究基金会;

关键词：

Memory interface; on-chip link; silicon interposer; transceiver; wireline;

D O I：

10.1109/JSSC.2014.2336213

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An energy-efficient 3 Gb/s current-mode interface scheme is proposed for on-chip global interconnects and silicon interposer channels. The transceiver core consists of an open-drain transmitter with one-tap pre-emphasis and a current sense amplifier load as the receiver. The current sense amplifier load is formed by stacking a PMOS diode stage and a cross-coupled NMOS stage, providing an optimum current-mode receiver without any bias current. The proposed scheme is verified with two cases of transceivers implemented in 65 nm CMOS. A 10 mm point-to-point data-only channel shows an energy efficiency of 9.5 fJ/b/mm, and a 20 mm four-drop source-synchronous link achieves 29.4 fJ/b/mm including clock and data channels.

引用

页码：2044 / 2053

页数：10

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