Thin silicon layer p-channel SOI/PSOI LDMOS with n+-islands for high voltage application

被引：6
作者：
Hu, Shengdong [1 ,2 ]
Zhu, Zhi [1 ]
Wu, Xinghe [1 ]
Jin, Jingjing [1 ]
Chen, Yinhui [1 ]
机构：
[1] Chongqing Univ, Coll Commun Engn, Chongqing 400044, Peoples R China
[2] 24 Res Inst China Elect Technol Grp Corp, Natl Lab Analogue Integrated Circuits, Chongqing, Peoples R China
来源：
SUPERLATTICES AND MICROSTRUCTURES | 2014年 / 67卷
基金：
中国博士后科学基金;
关键词：
P-channel LDMOS; SOI; Breakdown voltage; Interface charges; COMPOUND BURIED LAYER; PARTIAL-SOI LDMOSFET; BREAKDOWN VOLTAGE; PMOS TRANSISTOR; ELECTRIC-FIELD; TECHNOLOGY; IMPROVEMENT; OPTIMIZATION; RELIABILITY; CHARGES;
D O I：
10.1016/j.spmi.2013.11.027
中图分类号：
O469 [凝聚态物理学];
学科分类号：
070205 ;
摘要：
A novel thin silicon layer p-channel SOI/PSOI LDMOS with interface n(+)-islands (INI PLDMOS) is studied in this paper. Interface n(+)-islands can not only accumulate interface charges to enhance the electric field of buried oxide layer (BOX) (E-BOX) and achieve a high breakdown voltage (BV), but also form double-RESURF effect with p- drift region and improve the trade-off of the specific on-resistance (R-on,R-sp) and BV. The work mechanism of the proposed p-channel LDMOS is discussed. BV > 1000 V is obtained for the INI PLDMOS based on a 1.5-mu n silicon layer and 2-mu m BOX. (C) 2013 Elsevier Ltd. All rights reserved.
引用
收藏
页码：1 / 7
页数：7
相关论文
共 25 条
  • [11] New high-voltage (> 1200 V) MOSFET with the charge trenches on partial SOI
    Luo, Xiaorong
    Zhang, Bo
    Li, Zhaoji
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2008, 55 (07) : 1756 - 1761
  • [12] A new structure and its analytical model for the electric field and breakdown voltage of SOI high voltage device with variable-k dielectric buried layer
    Luo, Xiaorong
    Zhang, Bo
    Li, Zhaoji
    [J]. SOLID-STATE ELECTRONICS, 2007, 51 (03) : 493 - 499
  • [13] Realization of High Voltage (> 700 V) in New SOI Devices With a Compound Buried Layer
    Luo, Xiaorong
    Li, Zhaoji
    Zhang, Bo
    Fu, Daping
    Zhan, Zhan
    Chen, Kaifeng
    Hu, Shengdong
    Zhang, Zhengyuan
    Feng, Zhicheng
    Yan, Bin
    [J]. IEEE ELECTRON DEVICE LETTERS, 2008, 29 (12) : 1395 - 1397
  • [14] Injected charges in partial SOI LDMOSFETs: A new technique for improving the breakdown voltage
    Mehrad, Mahsa
    Orouji, Ali A.
    [J]. SUPERLATTICES AND MICROSTRUCTURES, 2013, 57 : 77 - 84
  • [15] Miyoshi T, 2013, PROC INT SYMP POWER, P393, DOI 10.1109/ISPSD.2013.6694428
  • [16] A novel partial SOI LDMOSFET with a trench and buried P layer for breakdown voltage improvement
    Orouji, Ali A.
    Mahabadi, S. E. Jamali
    Keshavarzi, P.
    [J]. SUPERLATTICES AND MICROSTRUCTURES, 2011, 50 (05) : 449 - 460
  • [17] A New Partial-SOI LDMOSFET With Modified Electric Field for Breakdown Voltage Improvement
    Orouji, Ali A.
    Sharbati, Samaneh
    Fathipour, Morteza
    [J]. IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2009, 9 (03) : 449 - 453
  • [18] Paul A K, 1996, P 8 INT S POW SEM DE, P89
  • [19] 300-V High-Side Thin-Layer-SOI Field pLDMOS With Multiple Field Plates Based on Field Implant Technology
    Qiao, Ming
    Zhou, Xin
    He, Yitao
    Wen, Hengjuan
    Zhao, Yuanyuan
    Zhang, Bo
    Li, Zhaoji
    [J]. IEEE ELECTRON DEVICE LETTERS, 2012, 33 (10) : 1438 - 1440
  • [20] Two-dimensional analytical subthreshold model of graded channel DG FD SOI n-MOSFET with gate misalignment effect
    Sharma, Rupendra Kumar
    Gupta, Mridula
    Gupta, R. S.
    [J]. SUPERLATTICES AND MICROSTRUCTURES, 2009, 45 (03) : 91 - 104
123