Thin silicon layer p-channel SOI/PSOI LDMOS with n+-islands for high voltage application

被引：6
作者：
Hu, Shengdong [1 ,2 ]
Zhu, Zhi [1 ]
Wu, Xinghe [1 ]
Jin, Jingjing [1 ]
Chen, Yinhui [1 ]
机构：
[1] Chongqing Univ, Coll Commun Engn, Chongqing 400044, Peoples R China
[2] 24 Res Inst China Elect Technol Grp Corp, Natl Lab Analogue Integrated Circuits, Chongqing, Peoples R China
来源：
SUPERLATTICES AND MICROSTRUCTURES | 2014年 / 67卷
基金：
中国博士后科学基金;
关键词：
P-channel LDMOS; SOI; Breakdown voltage; Interface charges; COMPOUND BURIED LAYER; PARTIAL-SOI LDMOSFET; BREAKDOWN VOLTAGE; PMOS TRANSISTOR; ELECTRIC-FIELD; TECHNOLOGY; IMPROVEMENT; OPTIMIZATION; RELIABILITY; CHARGES;
D O I：
10.1016/j.spmi.2013.11.027
中图分类号：
O469 [凝聚态物理学];
学科分类号：
070205 ;
摘要：
A novel thin silicon layer p-channel SOI/PSOI LDMOS with interface n(+)-islands (INI PLDMOS) is studied in this paper. Interface n(+)-islands can not only accumulate interface charges to enhance the electric field of buried oxide layer (BOX) (E-BOX) and achieve a high breakdown voltage (BV), but also form double-RESURF effect with p- drift region and improve the trade-off of the specific on-resistance (R-on,R-sp) and BV. The work mechanism of the proposed p-channel LDMOS is discussed. BV > 1000 V is obtained for the INI PLDMOS based on a 1.5-mu n silicon layer and 2-mu m BOX. (C) 2013 Elsevier Ltd. All rights reserved.
引用
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页码：1 / 7
页数：7
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