MALMM: A multi-array architecture for large-scale matrix multiplication on FPGA

被引：4

作者：

Huang, You ^{[1
,2
]}

Shen, Junzhong ^{[1
,2
]}

Qiao, Yuran ^{[1
,2
]}

Wen, Mei ^{[1
,2
]}

Zhang, Chunyuan ^{[1
,2
]}

机构：

[1] Natl Univ Def Technol, Coll Comp, Changsha 410073, Hunan, Peoples R China

[2] Natl Univ Def Technol, Natl Key Lab Parallel & Distributed Proc, Changsha 410073, Hunan, Peoples R China

来源：

IEICE ELECTRONICS EXPRESS | 2018年 / 15卷 / 10期

关键词：

matrix multiplication; field-programmable gate arrays (FPGAs); work-stealing;

D O I：

10.1587/elex.15.20180286

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Large-scale floating-point matrix multiplication is widely used in many scientific and engineering applications. Most existing works focus on designing a linear array architecture for accelerating matrix multiplication on FPGAs. This paper towards the extension of this architecture by proposing a scalable and highly configurable multi-array architecture. In addition, we present a work-stealing scheme to ensure the equality in the workload partition among multiple linear arrays. Furthermore, an analytical model is developed to determine the optimal parameters for matrix multiplication acceleration. Experiments on real-life convolutional neural networks (CNNs) show that we can obtain the optimal extension of the linear array architecture.

引用

页数：12