A unified approach to Boolean function decomposition for multilevel FPGA-based design

被引：0

作者：

Boole, E ^{[1
]}

Boule, K ^{[1
]}

Chapenko, V ^{[1
]}

机构：

[1] Latvian State Univ, Inst Elect & Comp Sci, LV-1063 Riga, Latvia

来源：

PROGRAMMABLE DEVICES AND SYSTEMS 2001 | 2002年

关键词：

combinational circuits; truth tables; decomposition method; design VLSI; multilevel structures;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

The paper is focussed on a method for constructing decomposition for Boolean function multilevel realizations based on field programmable gate arrays (FPGA). The method is based on formulating the criterion of compatibility for subsets of atomic requirements, which are defined by an initial function truth table. This criterion enables one to obtain simultaneously both input variables distribution and truth tables for all subsystems, which will be mapped to FPGA's cells of a single level of the multilevel realization. Particular restrictions for the subsets of compatibility allow to construct realization from input to output, from output to input, and to get disjunctive and conjunctive decompositions for the case of non-universal cells. The method is illustrated by examples. Copyright (C) 2001 IFAC.

引用

页码：215 / 219

页数：5

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