Efficient wordlength reduction techniques for DSP applications

Intermediate results in digital signal processing (DSP) hardware frequently must be truncated or rounded to maintain reasonable wordlengths. Noise and bias are introduced into the signal due to these operations. For the addition operation, we investigate two methods which have reduced variance and bias and yet maintain the computational simplicity of truncation. Essentially, each method drives the least significant carry input of the adder string with a very simple boolean function. We demonstrate the utility of these approaches by calculating bias and variance reductions, and by using the methods in several simple but important DSP examples.