Hierarchical Boundary-Scan a Scan Chip-Set solution

被引：4

作者：

Harrison, S ^{[1
]}

Noeninckx, G ^{[1
]}

Horwood, P ^{[1
]}

Collins, P ^{[1
]}

机构：

[1] Motorola Inc, Schaumburg, IL 60196 USA

来源：

INTERNATIONAL TEST CONFERENCE 2001, PROCEEDINGS | 2001年

关键词：

D O I：

10.1109/TEST.2001.966665

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The Boundary-Scan IEEE1149.1 Std, has become an important design criterion with complex IC's and Board designs within Motorola's Infrastructure products. This paper describe the "Boundary-Scan Chip-Set" that has been developed by Motorola and its component and test solution providers to enable a comprehensive boundary-scan test strategy at all levels of product build, board, system and field. The "Boundary-Scan Chip Set" allows hierarchical and multi-drop Boundary-Scan test architectures to be applied at all levels of product build. The "Boundary-Scan Chip-Set" consists of 3 distinct functions a "Bridge" a "Scan- Controller" and a "BIST-Sequencer". The "Bridge" enables a hierarchical multi-drop IEEE1149.1 Boundary-Scan implementation within a backplane configuration, whilst the " ScanController" provides the necessary processor and memory interface for in-system Boundary-Scan test vectors and commands to be broadcast to slave cards within the backplane configuration. The "BIST-Sequencer" enables locally stored test vectors and commands to be executed and analyzed without on-board processor control. The Scan Chip-Set family of devices is now incorporated into Motorola infrastructure product, enhancing and improving both factory and field testability and diagnostics.

引用

页码：480 / 486

页数：7