A low power high accuracy CMOS time-to-digital converter

In this paper, we present a new CMOS time-to-digital converter (TDC) with the cyclic delay line structure. The static supply current is 2-nA only. Furthermore, the continuous calibration is no longer needed. The TDC can be shunt down between measurements to make the power consumption negligible. The circuit with 64-stage cyclic delay line has been fitted into 0.25mm x 0.75mm chip area with a typical 0.8-mu m SPDM process. The measured resolution is 286 picoseconds, and the measured single-shot accuracy is less than 143 picoseconds. Both can be made much less if the control voltage is well tuned.