A low power high accuracy CMOS time-to-digital converter

被引：0
|
作者：
Chen, PK
Liu, SI
Wu, JS
机构：
来源：
ISCAS '97 - PROCEEDINGS OF 1997 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I - IV: CIRCUITS AND SYSTEMS IN THE INFORMATION AGE | 1997年
关键词：
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
In this paper, we present a new CMOS time-to-digital converter (TDC) with the cyclic delay line structure. The static supply current is 2-nA only. Furthermore, the continuous calibration is no longer needed. The TDC can be shunt down between measurements to make the power consumption negligible. The circuit with 64-stage cyclic delay line has been fitted into 0.25mm x 0.75mm chip area with a typical 0.8-mu m SPDM process. The measured resolution is 286 picoseconds, and the measured single-shot accuracy is less than 143 picoseconds. Both can be made much less if the control voltage is well tuned.
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页码：281 / 284
页数：4
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