A low power wide tuning range two stage ring VCO with frequency enhancing

被引：5

作者：

Yan, Chenggang ^{[1
]}

Wu, Jianhui ^{[1
]}

Hu, Chen ^{[1
]}

Ji, Xincun ^{[2
]}

机构：

[1] Southeast Univ, Nanjing 210096, Jiangsu, Peoples R China

[2] Nanjing Univ Posts & Telecommun, Nanjing 210023, Jiangsu, Peoples R China

来源：

IEICE ELECTRONICS EXPRESS | 2019年 / 16卷 / 08期

基金：

中国国家自然科学基金;

关键词：

voltage controlled oscillator; wide tuning range; low power; PHASE-NOISE; PLL;

D O I：

10.1587/elex.16.20190090

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A wide tuning range frequency enhanced two stage ring voltage controlled oscillator (VCO) is proposed in this letter. The proposed delay cell increases the transmission gain by inserting a resistor between input and output, which consumes lower power to generate same oscillating frequency. A rail-to-rail effective voltage tuning range is obtained by both tuning of tail current and the strength of cross coupled latch. It is important for advanced process, which has low standard supply voltage and high threshold voltage. The proposed VCO is fabricated in TSMC 40 nm CMOS technology. The measured phase noise of proposed VCO is -98.05 dBc/Hz at 1 MHz offset with 1.38 GHz carrier frequency while consuming 1.1 mW from a 1.1 V standard supply. The figure of merit (FoM) is 160.4 dBc/Hz.

引用

页数：4

共 31 条

[1] Design of a 60-GHz receiver front-end with broadband matching techniques in 65-nm CMOS [J].

Chai, Yuan ;

Li, Lianming ;

Cui, Tiejun .

IEICE ELECTRONICS EXPRESS, 2018, 15 (24)

[2]

Chen K., 2014, IEEE C EL DEV SOL ST, DOI [10.1109/EDSSC.2014.7061153, DOI 10.1109/EDSSC.2014.7061153]

[3] A 0.5-V, 440-μW Frequency Synthesizer for Implantable Medical Devices [J].

Chen, Wu-Hsin ;

Loke, Wing-Fai ;

Jung, Byunghoo .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2012, 47 (08) :1896-1907

[4] A burst-mode clock and data recovery circuit with two symmetric quadrature VCO's [J].

Choi, Bum-Hee ;

Son, Kyung-Sub ;

An, Taek-Joon ;

Kang, Jin-Ku .

IEICE ELECTRONICS EXPRESS, 2016, 13 (24) :1-8

[5] Sub-1V V-I converter-based voltage-controlled oscillator with a linear gain characteristic [J].

Choi, HyungJin ;

Min, Young-Jae ;

Ko, Jaehong ;

Han, Miseon ;

Han, Youngsun .

IEICE ELECTRONICS EXPRESS, 2017, 14 (15)

[6] A 28-GHz Quadrature Fractional-N Frequency Synthesizer for 5G Transceivers With Less Than 100-fs Jitter Based on Cascaded PLL Architecture [J].

El-Halwagy, Waleed ;

Nag, Amlan ;

Hisayasu, Philip ;

Aryanfar, Farshid ;

Mousavi, Pedram ;

Hossain, Masum .

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, 2017, 65 (02) :396-413

[7] A 2.0-5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider [J].

Elkholy, Ahmed ;

Saxena, Saurabh ;

Nandwana, Romesh Kumar ;

Elshazly, Amr ;

Hanumolu, Pavan Kumar .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2016, 51 (08) :1771-1784

[8] An Adaptive Bitrate Clock and Data Recovery Circuit for Communication Signal Analyzers [J].

Guerrero, E. ;

Sanchez-Azqueta, C. ;

Gimeno, C. ;

Aguirre, J. ;

Celma, S. .

IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, 2017, 66 (01) :191-193

[9] Jitter and phase noise in ring oscillators [J].

Hajimiri, A ;

Limotyrakis, S ;

Lee, TH .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1999, 34 (06) :790-804

[10] A SiGe Fractional-N Frequency Synthesizer for mm-Wave Wideband FMCW Radar Transceivers [J].

Hasenaecker, Gregor ;

van Delden, Marcel ;

Jaeschke, Timo ;

Pohl, Nils ;

Aufinger, Klaus ;

Musch, Thomas .

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, 2016, 64 (03) :847-858

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