Development of Bonding Process for High Density Fine Pitch Micro Bump Interconnections with Wafer Level Underfill for 3D Applications

Realization of 3D IC packaging is mainly depends on the success of fine pitch micro bump bonding process for thin chips stacking and reliability of micro bump interconnections between stacked chips. The uniformity of micro bumps is the critical requirement to achieve good micro bump bonding, and the chip warpage during bonding and underfilling of micro gaps between stacked chips is key challenge in 3D IC packaging. In this work, The FEM modeling and simulations has been carried out to understand the effect of the package parametric on chip warpage and results revealed that chip thickness and substrate thickness has significant effect on chip warpage. The warpage of the test chip with TSVs is lower when compared to test vehicle without TSVs. The fabrication process has been optimized to achieve uniform high density fine pitch micro bumps of 10 mu m diameter at 20 mu m pitch. Flip chip bonding processes for 20 mu m pitch micro bumps with and without pre-applied wafer level underfill material are optimized using conventional reflow and thermal compression bonding (TCB) respectively. Capillary underfill process is also optimized for micro gaps of less than 20 mu m and achieved void free underfilling. Thermal compression bonding temperature and force profiles are optimized for micro bumps with pre-applied wafer level underfill material, and achieved good micro bump joints with void free underlining. Cross-sectional analysis revealed good micro bump joints with and without pre-applied underfill materials and CSAM analysis revealed void free underfilling is feasible using capillary underfilling as well as TCB with pre-applied wafer level underfill. Finally, this paper demonstrated bonding process for high density fine pitch micro bumps for thin large chips stacking which required for 3D IC packaging application.