A low-jitter 1.9-V CMOS PLL for UltraSPARC microprocessor applications

A phase-locked Loop (PLL) for CMOS UltraSPARC microprocessor applications uses a loop filter referenced to a quiet power supply and achieves measured clock period jitter of +/- 25 ps at 360 MHz. The fully integrated CMOS PLL uses a charge-pump phase/frequency detector, a single-capacitor loop filter, and a feed-forward error correction architecture. Loop characteristics are analyzed and verified by measurements. The measured sensitivity of clock period jitter to supply voltage is 2.6 ps/100 my over an analog supply-voltage range of 1.6-2.1 V; the measured output operating frequency range is 8.5-660 MHz. Fabricated in an area of 310 x 280 mu m(2) in a 0.25-mu m CMOS process, the PLL dissipates 25 mW from a 1.9-V supply.