A simulator for evaluating redundancy analysis algorithms of repairable embedded memories

被引：32

作者：

Huang, RF ^{[1
]}

Li, JF ^{[1
]}

Yeh, JC ^{[1
]}

Wu, CW ^{[1
]}

机构：

[1] Natl Tsing Hua Univ, Dept Elect Engn, Lab Reliable Comp LARC, Hsinchu 30013, Taiwan

来源：

PROCEEDING OF THE 2002 IEEE INTERNATIONAL WORKSHOP ON MEMORY TECHNOLOGY, DESIGN AND TESTING | 2002年

关键词：

embedded memory; memory testing; memory repair; redundancy analysis; simulation;

D O I：

10.1109/MTDT.2002.1029766

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We present a simulator for evaluating the redundancy analysis (RA) algorithms. The simulator can calculate the repair rate (the ratio of the number of repaired memories to the number of defective memories) of the given RA algorithm and the associated memory configuration and redundancy structure. With the tool, the user also can easily assess and plan the redundant (spare) elements, and subsequently develop the built-in redundancy analysis (BIRA) algorithms and circuits that are essential for built-in self-repair (BISR) of embedded memories. The simulator has another important feature-it can simulate the sequence of the detected faults in the real order improving the accuracy of the analysis results.

引用

页码：68 / 73

页数：6

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