Double Node Upsets Hardened Latch Circuits

被引：74

作者：

Li, Yuanqing ^{[1
]}

Wang, Haibin ^{[1
,2
]}

Yao, Suying ^{[3
]}

Yan, Xi ^{[3
]}

Gao, Zhiyuan ^{[3
]}

Xu, Jiangtao ^{[3
]}

机构：

[1] Univ Saskatchewan, Dept Elect & Comp Engn, Saskatoon, SK, Canada

[2] Hohai Univ, Coll IOT Engn, Changzhou, Peoples R China

[3] Tianjin Univ, Sch Elect Informat Engn, Tianjin 300072, Peoples R China

来源：

JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS | 2015年 / 31卷 / 5-6期

关键词：

Double node upsets; Latch; RHBD; Setup time; Temporal hardening; SINGLE-EVENT; PROPAGATION; DESIGN;

D O I：

10.1007/s10836-015-5551-3

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A radiation hardened by design (RHBD) latch and its temporally hardened version to tolerate double node upsets are proposed in this paper. C-Elements are used to construct structures for fault correction. The temporally hardened version can further tolerate some single-event transients (SETs) at input port and clock line. Compared with Quintuple Modular Redundancy (QMR), the proposed non-temporally and temporally hardened latches are more area and power efficient with improved propagation delays. Compared with several previously reported temporally hardened latches, the proposed temporally hardened latch may introduce lower performance loss induced as setup time increase. Several multi-node upset tolerant latches are also compared with these two designs in terms of area, power, and delay. A cell level soft error analysis (TFIT) shows that the upset threshold LETs of the proposed latches in 180 nm process are higher than 16 MeV-cm(2)/mg.

引用

页码：537 / 548

页数：12

共 25 条

[1] Charge collection and charge sharing in a 130 nm CMOS technology [J].

Amusan, Oluwole A. ;

Witulski, Arthur F. ;

Massengill, Lloyd W. ;

Bhuva, Bharat L. ;

Fleming, Patrick R. ;

Alles, Michael L. ;

Sternberg, Andrew L. ;

Black, Jeffrey D. ;

Schrimpf, Ronald D. .

IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2006, 53 (06) :3253-3258

[2] RHBD techniques for mitigating effects of single-event hits using guard-gates [J].

Balasubramanian, A ;

Bhuva, BL ;

Black, JD ;

Massengill, LW .

IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2005, 52 (06) :2531-2535

[3]

Baumann R. C., 2001, IEEE Transactions on Device and Materials Reliability, V1, P17, DOI 10.1109/7298.946456

[4] Design of a Nanometric CMOS Memory Cell for Hardening to a Single Event With a Multiple-Node Upset [J].

D'Alessio, Marco ;

Ottavi, Marco ;

Lombardi, Fabrizio .

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2014, 14 (01) :127-132

[5] Scaling Trends in SET Pulse Widths in Sub-100 nm Bulk CMOS Processes [J].

Gadlage, Matthew J. ;

Ahlbin, Jonathan R. ;

Narasimham, Balaji ;

Bhuva, Bharat L. ;

Massengill, Lloyd W. ;

Reed, Robert A. ;

Schrimpf, Ronald D. ;

Vizkelethy, Gyorgy .

IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2010, 57 (06) :3336-3341

[6] Comparison of heavy ion and proton induced combinatorial and sequential logic error rates in a deep submicron process [J].

Gadlage, MJ ;

Eaton, PH ;

Benedetto, JM ;

Turflinger, TL .

IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2005, 52 (06) :2120-2124

[7] Single-Event Upsets and Multiple-Bit Upsets on a 45 nm SOI SRAM [J].

Heidel, David F. ;

Marshall, Paul W. ;

Pellish, Jonathan A. ;

Rodbell, Kenneth P. ;

LaBel, Kenneth A. ;

Schwank, James R. ;

Rauch, Stewart E. ;

Hakey, Mark C. ;

Berg, Melanie D. ;

Castaneda, Carlos M. ;

Dodd, Paul E. ;

Friendlich, Mark R. ;

Phan, Anthony D. ;

Seidleck, Christina M. ;

Shaneyfelt, Marty R. ;

Xapsos, Michael A. .

IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2009, 56 (06) :3499-3504

[8]

iROC Technology, 2014, TFIT REF MAN SOFTW V

[9] Soft error interception latch: double node charge sharing SEU tolerant design [J].

Katsarou, K. ;

Tsiatouhas, Y. .

ELECTRONICS LETTERS, 2015, 51 (04) :330-331

[10]

Katsarou K, 2014, IEEE INT ON LINE, P122, DOI 10.1109/IOLTS.2014.6873683

← 1 2 3 →