Cost Model for Monolithic 3D Integrated Circuits

被引：0

作者：

Gitlin, Daniel ^{[1
]}

Vinet, Maud ^{[2
]}

Clermidy, Fabien ^{[2
]}

机构：

[1] CEA Leti, Palo Alto, CA 94306 USA

[2] CEA, LetiMINATEC Campus, 17 Rue Martyrs, Grenoble, France

来源：

2016 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S) | 2016年

关键词：

Cost; 3D IC; PPC; CoolCube (TM); Yield;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A cost model for monolithic 3D-ICs is presented that takes into account increased process complexity and associated yield impact as well as area reduction. The model enables more accurate PPC (Power, Performance and Cost) understanding and the range of applicability for monolithic 3D-IC technology. The model shows that depending on the die area and partitioning scheme, the cost benefit can be 50% or higher.

引用

页数：2