A Study on CMOS Time Uncertainty with Technology Scaling

被引：0

作者：

Figueiredo, Monica ^{[1
,3
]}

Aguiar, Rui L. ^{[2
,3
]}

机构：

[1] Escola Super Tecnol & Gestao, Inst Politecn Leiria, Aveiro, Portugal

[2] Univ Aveiro, Dept Elect & Telecommun, Aveiro, Portugal

[3] Inst Telecommun, Aveiro, Portugal

来源：

INTEGRATED CIRCUIT AND SYSTEMS DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION | 2009年 / 5349卷

关键词：

CMOS; Uncertainty; Noise; Jitter; Scaling; JITTER; NOISE;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper evaluates the clock generation quality of different digital circuits associated with clock generation and distribution. Circuit's noise response, jitter, and uncertainty are evaluated for different noise sources and loading conditions. We present performance simulations for inverters and inverter chains implemented in different technologies from AMS and UMC foundries. We show that the device size-scaling trend is increasing the uncertainty associated with this circuits, decreasing their precision. The correlation between circuit's parameters and selected performance metrics is also highlighted.

引用

页码：146 / +

页数：2

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