Optical Interposer Technology using Buried Vertical-Cavity Surface-Emitting Laser Chip and Tapered Through-Silicon Via for High-Speed Chip-to-Chip Optical Interconnection

被引：5

作者：

Noriki, Akihiro ^{[1
]}

Fujiwara, Makoto ^{[1
,2
]}

Lee, Kang-Wook ^{[1
]}

Jeong, Woo-Cheol ^{[1
]}

Fukushima, Takafumi ^{[1
]}

Tanaka, Tetsu ^{[1
]}

Koyanagi, Mitsumasa ^{[1
]}

机构：

[1] Tohoku Univ, Grad Sch Engn, Dept Bioengn & Robot, Aoba Ku, Sendai, Miyagi 9808579, Japan

[2] Sumitomo Bakelite Co Ltd, Totsuka Ku, Yokohama, Kanagawa 2450052, Japan

来源：

JAPANESE JOURNAL OF APPLIED PHYSICS | 2009年 / 48卷 / 04期

关键词：

Microoptics - Optical interconnects - Integrated circuit interconnects - Three dimensional integrated circuits - Silicon - Optical waveguides - Self assembly - Electronics packaging;

D O I：

10.1143/JJAP.48.04C113

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

A novel optical interposer with optical interconnections is proposed for integrating three-dimensional (3D) LSI chips on this interposer. Vertical-cavity surf ace-emit ring laser diode (VCSEL) chips and photo diode (PD) chips are buried in the optical interposer with polymeric optical waveguides. The VCSEL is 0.25 mm in width, 0.35 mm in length, and 0.15 mm in height. We realize precise passive alignment between the optical waveguides and the VCSEL/PD chips using two-step alignment processes consisting of cavity-assisted positioning and the subsequent surface-tension-powered self-assembly with a molten solder. In addition, we demonstrate the basic operation of the buried VCSEL chips in the optical interposer through tapered through-silicon vias (TSVs). The tapered TSVs are successfully formed by copper electroplating and are 64 mu m in top width, 34 mu m in bottom width, and 168 mu m in length. (C) 2009 The Japan Society of Applied Physics

引用

页数：5

共 50 条

[1] High-speed on-chip and chip-to-chip optical interconnection
Tsuda, H
Nakahara, T
FUNDAMENTAL PROBLEMS OF OPTOELECTRONICS AND MICROELECTRONICS, 2003, 5129 : 18 - 23
[2] Vertical-Cavity Surface-Emitting Laser Flip-Chip Bonding to Silicon Photonics Chip
Wang, Yun
Djordjecvic, Stevan S.
Yao, Jin
Cunningham, John E.
Zheng, Xuezhe
Krishnamoorthy, Ashok V.
Muller, Michael
Amann, Markus-Christian
Bojko, Richard
Jaeger, Nicolas A. F.
Chrostowski, Lukas
2015 IEEE OPTICAL INTERCONNECTS CONFERENCE, 2015, : 122 - 123
[3] Active interposer technology for high-speed and low-cost chip-to-chip optical interconnects
Mikawa, T
Ibaragi, O
Bonkohara, M
ACTIVE AND PASSIVE OPTICAL COMPONENTS FOR WDM COMMUNICATIONS II, 2002, 4870 : 430 - 436
[4] HIGH-SPEED VERTICAL-CAVITY SURFACE-EMITTING LASER
SHTENGEL, G
TEMKIN, H
BRUSENBACH, P
UCHIDA, T
KIM, M
PARSONS, C
QUINN, WE
SWIRHUN, SE
IEEE PHOTONICS TECHNOLOGY LETTERS, 1993, 5 (12) : 1359 - 1362
[5] Vertical-cavity surface-emitting laser and its applications for optical interconnection and switch
Kosaka, H
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 1998, 37 (3B): : 1394 - 1399
[6] Chip-level integrated diffractive optical microlenses for multimode vertical-cavity surface-emitting laser to fiber coupling
Ammer, T
Gale, MT
Rossi, M
OPTICAL ENGINEERING, 2002, 41 (12) : 3141 - 3150
[7] OPTICAL MEMORY USING A VERTICAL-CAVITY SURFACE-EMITTING LASER
HUFFAKER, DL
LEE, WD
DEPPE, DG
LEI, C
ROGERS, TJ
CAMPBELL, JC
STREETMAN, BG
IEEE PHOTONICS TECHNOLOGY LETTERS, 1991, 3 (12) : 1064 - 1066
[8] INTEGRATION OF A SINGLE VERTICAL-CAVITY SURFACE-EMITTING LASER ONTO A CMOS INVERTER CHIP
DARYANANI, S
FATHOLLAHNEJAD, H
MATHINE, DL
DROOPAD, R
KUBES, A
MARACAS, GN
ELECTRONICS LETTERS, 1995, 31 (10) : 833 - 834
[9] High-Speed Buried Tunnel Junction Vertical-Cavity Surface-Emitting Lasers
Hofmann, Werner
IEEE PHOTONICS JOURNAL, 2010, 2 (05): : 802 - 815
[10] High-speed 985 nm bottom-emitting VCSEL Arrays for chip-to-chip parallel optical interconnects
Lin, Chao-Kun
Tandon, Ashish
Djordjev, Kostadin
Corzine, Scott W.
Tan, Michael R. T.
IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, 2007, 13 (05) : 1332 - 1339

← 1 2 3 4 5 →