A secure exponentiation algorithm resistant to a combined attack on RSA implementation

被引:8
|
作者
Kim, HyeongDong [1 ]
Choi, YongJe [2 ]
Choi, DooHo [2 ]
Ha, JaeCheol [1 ]
机构
[1] Hoseo Univ, Dept Informat Secur, Asan 336795, Chungnam, South Korea
[2] Elect & Telecommun Res Inst, Daejeon 305700, South Korea
关键词
CRT-RSA algorithm; side-channel attack; combined attack; exponentiation; fault attack; 94A60; 14G50; 68P25; POWER ANALYSIS; CRT;
D O I
10.1080/00207160.2014.935353
中图分类号
O29 [应用数学];
学科分类号
070104 ;
摘要
Because two types of side-channel attacks, namely passive information leakages and active fault injections, are considered separate implementation threats to cryptographic modules, most countermeasures against these attacks have been independently developed. However, Amiel et al. demonstrated that a fault injection combined with a simple power analysis (SPA) can break such a classical Rivest, Shamir, and Adelman (RSA) system implementation. In this paper, we show that this combined attack (CA) can be applied to the Boscher, Naciri, and Prouff algorithm, which is an SPA/fault attack (FA)-resistant exponentiation method for RSA implementation. Furthermore, this paper proposes a novel exponentiation algorithm resistant to power analysis and an FA as well as to the CA. The proposed exponentiation algorithm can be employed for secure Chinese remainder theorem-RSA implementation. In addition, the paper presents some experimental results of an SPA under the assumption of a successful fault injection.
引用
收藏
页码:258 / 272
页数:15
相关论文
共 34 条
  • [31] Chosen Ciphertext Combined Attack Based on Round-Reduced Fault Against SM2 Decryption Algorithm
    Li H.-Y.
    Han X.-C.
    Cao W.-Q.
    Wang J.
    Chen H.
    Tien Tzu Hsueh Pao/Acta Electronica Sinica, 2023, 51 (11): : 3187 - 3198
  • [32] A Shared Key Recovery Attack on a Masked Implementation of CRYSTALS-Kyber's Encapsulation Algorithm
    Wang, Ruize
    Dubrova, Elena
    FOUNDATIONS AND PRACTICE OF SECURITY, PT I, FPS 2023, 2024, 14551 : 424 - 439
  • [33] BLAKE-512-Based 128-Bit CCA2 Secure Timing Attack Resistant McEliece Cryptoprocessor
    Ghosh, Santosh
    Verbauwhede, Ingrid
    IEEE TRANSACTIONS ON COMPUTERS, 2014, 63 (05) : 1124 - 1133
  • [34] A Time-/Frequency-Domain Side-Channel Attack Resistant AES-128 and RSA-4K Crypto-Processor in 14-nm CMOS
    Kumar, Raghavan
    Liu, Xiaosen
    Suresh, Vikram
    Krishnamurthy, Harish K.
    Satpathy, Sudhir
    Anders, Mark A.
    Kaul, Himanshu
    Ravichandran, Krishnan
    De, Vivek
    Mathew, Sanu K.
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2021, 56 (04) : 1141 - 1151