Random Threshold Voltage Variability Induced by Gate-Edge Fluctuations in Nanoscale Metal-Oxide-Semiconductor Field-Effect Transistors

被引：31

作者：

Putra, Arifin Tamsir ^{[1
]}

Nishida, Akio ^{[2
]}

Kamohara, Shiro ^{[2
]}

Hiramoto, Toshiro ^{[1
,2
]}

机构：

[1] Univ Tokyo, Inst Ind Sci, Meguro Ku, Tokyo 1538505, Japan

[2] MIRAI Selete, Tsukuba, Ibaraki 3058569, Japan

来源：

APPLIED PHYSICS EXPRESS | 2009年 / 2卷 / 02期

关键词：

LINE; ROUGHNESS;

D O I：

10.1143/APEX.2.024501

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

A very rapid method of estimating the effect of gate-edge fluctuation on threshold voltage (V-th) variability in metal-oxide-semiconductor field-effect transistors (MOSFETs) is proposed. An empirical model is developed, in which correlation width (W-c) from gate line-width roughness (LWR) is a key parameter of the model. The validity of the model is confirmed using the measured data and an autoregressive model. Wc is extracted from the gate line-edge shape depicted in a scanning electron microscope (SEM) image. This method is very useful for the intuitive understanding of the gate-edge fluctuation effect on V-th variability. (C) 2009 The Japan Society of Applied Physics

引用

页数：3

共 10 条

[1] Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness [J].

Asenov, A ;

Kaya, S ;

Brown, AR .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2003, 50 (05) :1254-1260

[2]

Croon JA, 2002, INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST, P307, DOI 10.1109/IEDM.2002.1175840

[3]

Hane M, 2003, 2003 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST, P241

[4] Full spectral analysis of line width roughness [J].

Leunissen, LHA ;

Lorusso, GF ;

Ercken, M ;

Croon, JA ;

Yang, H ;

Azordegan, A ;

DiBiase, T .

METROLOGY, INSPECTION, AND PROCESS CONTROL FOR MICROLITHOGRAPHY XIX, PTS 1-3, 2005, 5752 :499-509

[5] Line edge roughness: experimental results related to a two-parameter model [J].

Leunissen, LHA ;

Lawrence, WG ;

Ercken, M .

MICROELECTRONIC ENGINEERING, 2004, 73-4 :265-270

[6]

LINTON T, 1999, IEEE SIL NAN WORKSH, P28

[7] Modeling line edge roughness effects in sub 100 nanometer gate length devices [J].

Oldiges, P ;

Lin, QH ;

Petrillo, K ;

Sanchez, M ;

Ieong, M ;

Hargrove, M .

2000 INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES, 2000, :131-134

[8] MATCHING PROPERTIES OF MOS-TRANSISTORS [J].

PELGROM, MJM ;

DUINMAIJER, ACJ ;

WELBERS, APG .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1989, 24 (05) :1433-1440

[9]

Tsunomura T, 2008, S VLSI TECH, P121, DOI 10.1109/VLSIT.2008.4588600

[10] Characterization of line-edge roughness in resist patterns and estimation of its effect on device performance [J].

Yamaguchi, A ;

Tsuchiya, R ;

Fukuda, H ;

Komuro, O ;

Kawada, H ;

Iizumi, T .

METROLOGY, INSPECTION, AND PROCESS CONTROL FOR MICROLITHOGRAPHY XVII, PTS 1 AND 2, 2003, 5038 :689-698

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