A 10-BIT 800MS/S LOW POWER TIME-INTERLEAVED SAR ADC WITH BACKGROUND CALIBRATION

被引：0
|
作者：
Pu, Jie [1 ]
Xu, Daiguo [1 ]
Wang, Yuxin [1 ]
Zhang, Ruitao [1 ]
机构：
[1] Sci & Technol Analog Integrated Circuit Lab, Chongqing 400060, Peoples R China
来源：
2016 13TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT) | 2016年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A power- and area-efficient time-interleaved ADC employs eight successive-approximation-register (SAR) time-interleaved channels along with a new timing mismatch detection algorithm. The digital background calibration technique suppresses the inter-channel offset, gain and timing mismatches. It consumes 15.718mA at 1.2V supply and 2 mA at 1.8V supply leading to a FOM of 13.6fJ/conversion-step in 55nm CMOS technology. Post layout simulation concerned noise achieves an ENOB of 9.66 at 10MHz input. Behavioral simulations show SFDR at 286.3MHz input can be improved from-40dB to-72dB after calibration.
引用
收藏
页码：1470 / 1472
页数：3
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