A 10-BIT 800MS/S LOW POWER TIME-INTERLEAVED SAR ADC WITH BACKGROUND CALIBRATION

被引：0

作者：

Pu, Jie ^{[1
]}

Xu, Daiguo ^{[1
]}

Wang, Yuxin ^{[1
]}

Zhang, Ruitao ^{[1
]}

机构：

[1] Sci & Technol Analog Integrated Circuit Lab, Chongqing 400060, Peoples R China

来源：

2016 13TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT) | 2016年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A power- and area-efficient time-interleaved ADC employs eight successive-approximation-register (SAR) time-interleaved channels along with a new timing mismatch detection algorithm. The digital background calibration technique suppresses the inter-channel offset, gain and timing mismatches. It consumes 15.718mA at 1.2V supply and 2 mA at 1.8V supply leading to a FOM of 13.6fJ/conversion-step in 55nm CMOS technology. Post layout simulation concerned noise achieves an ENOB of 9.66 at 10MHz input. Behavioral simulations show SFDR at 286.3MHz input can be improved from-40dB to-72dB after calibration.

引用

页码：1470 / 1472

页数：3

共 50 条

[21] A low power time-interleaved 10-bit 250-MSPS charge domain pipelined ADC for IF sampling
陈珍海
钱宏文
黄嵩人
张鸿
于宗光
Journal of Semiconductors, 2013, 34 (06) : 118 - 125
[22] A 2.3 mW 10-bit 170 MS/s Two-Step Binary-Sarch Assisted Time-Interleaved SAR ADC
Wong, Si-Seng
Chio, U-Fat
Zhu, Yan
Sin, Sai-Weng
U, Seng-Pan
Martins, Rui Paulo
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2013, 48 (08) : 1783 - 1794
[23] A 10-bit 320MS/s Time-Interleaved SAR ADC with an Improved Binary-Scaled Recombination Weighting Capacitor Array
Zhang, Xiaoyuan
Zhang, Yi
Ji, Xincun
Liu, Zhonghua
Xiao, Jian
Guo, Yufeng
2019 IEEE 4TH INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUITS AND MICROSYSTEMS (ICICM 2019), 2019, : 57 - 60
[24] IC design of 2Ms/s 10-bit SAR ADC with low power
Jun, Cai
Feng, Ran
Mei-Hua, Xu
HDP'07: PROCEEDINGS OF THE 2007 INTERNATIONAL SYMPOSIUM ON HIGH DENSITY PACKAGING AND MICROSYSTEM INTEGRATION, 2007, : 418 - +
[25] A CMOS 15-bit 125-MS/s time-interleaved ADC with digital background. calibration
Lee, Zwei-Mei
Wang, Cheng-Yeh
Wu, Jieh-Tsorng
PROCEEDINGS OF THE IEEE 2006 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2006, : 209 - 212
[26] A low-power, 6-bit time-interleaved SAR ADC using OFDM pilot tone calibration
Oh, Yangjin
Murmann, Boris
PROCEEDINGS OF THE IEEE 2007 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2007, : 193 - 196
[27] A Time-Interleaved SAR ADC With Signal-Independent Background Timing Calibration
Su, Christopher K.
Hurst, Paul J.
Lewis, Stephen H.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2022, 69 (02) : 620 - 633
[28] A 6 bit 2 GS/s Flash-Assisted Time-Interleaved (FATI) SAR ADC with Background Offset Calibration
Sung, Ba-Ro-Saim
Lee, Chang-Kyo
Kim, Wan
Kim, Jong-In
Hong, Hyeok-Ki
Oh, Ghil-Geun
Lee, Choong-Hoon
Choi, Michael
Park, Ho-Jin
Ryu, Seung-Tak
PROCEEDINGS OF THE 2013 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC), 2013, : 281 - 284
[29] A 10-bit 16-MS/s Ultra Low Power SAR ADC for IoT Applications
Yan, Na
Kang, Cheng
Mu, Geng
Chen, Sizheng
Wang, Maodong
Min, Hao
2018 14TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2018, : 759 - 761
[30] A 10-b 800-MS/s Time-Interleaved SAR ADC With Fast Variance-Based Timing-Skew Calibration
Song, Jeonggoo
Ragab, Kareem
Tang, Xiyuan
Sun, Nan
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2017, 52 (10) : 2563 - 2575

← 1 2 3 4 5 →