机构:
Univ Elect Sci & Technol China, Sch Elect Engn, Chengdu, Sichuan, Peoples R ChinaUniv Elect Sci & Technol China, Sch Elect Engn, Chengdu, Sichuan, Peoples R China
Zou, Lin
[1
]
Qian, Lu
论文数: 0引用数: 0
h-index: 0
机构:
Univ Elect Sci & Technol China, Sch Elect Engn, Chengdu, Sichuan, Peoples R ChinaUniv Elect Sci & Technol China, Sch Elect Engn, Chengdu, Sichuan, Peoples R China
Qian, Lu
[1
]
He, Rongjiang
论文数: 0引用数: 0
h-index: 0
机构:
Univ Elect Sci & Technol China, Sch Elect Engn, Chengdu, Sichuan, Peoples R ChinaUniv Elect Sci & Technol China, Sch Elect Engn, Chengdu, Sichuan, Peoples R China
He, Rongjiang
[1
]
Zhang, Chengfa
论文数: 0引用数: 0
h-index: 0
机构:
Univ Elect Sci & Technol China, Sch Elect Engn, Chengdu, Sichuan, Peoples R ChinaUniv Elect Sci & Technol China, Sch Elect Engn, Chengdu, Sichuan, Peoples R China
Zhang, Chengfa
[1
]
Jiang, Shuailong
论文数: 0引用数: 0
h-index: 0
机构:
Univ Elect Sci & Technol China, Sch Elect Engn, Chengdu, Sichuan, Peoples R ChinaUniv Elect Sci & Technol China, Sch Elect Engn, Chengdu, Sichuan, Peoples R China
Jiang, Shuailong
[1
]
Zhou, Yun
论文数: 0引用数: 0
h-index: 0
机构:
Univ Elect Sci & Technol China, Sch Elect Engn, Chengdu, Sichuan, Peoples R ChinaUniv Elect Sci & Technol China, Sch Elect Engn, Chengdu, Sichuan, Peoples R China
Zhou, Yun
[1
]
机构:
[1] Univ Elect Sci & Technol China, Sch Elect Engn, Chengdu, Sichuan, Peoples R China
来源:
PROCEEDINGS OF 2017 3RD IEEE INTERNATIONAL CONFERENCE ON COMPUTER AND COMMUNICATIONS (ICCC)
|
2017年
关键词:
radar seeker;
infield test system;
radar return simulator;
system scheme;
D O I:
暂无
中图分类号:
TP301 [理论、方法];
学科分类号:
081202 ;
摘要:
For the development of radar seekers, it is essential to build up an infield test system, whose key part is a real-time radar return simulator. At present, digital radio frequency memory (DRFM) structure has been more widely used in the radar return simulator. This paper presents a wideband radar return simulator based on DRFM. This simulator comprises radio frequency (RF) front-end, high speed analog to digital convertor (ADC) and digital to analog convertor (DAC), and large scale field programmable gate array (FPGA). Design aspects are discussed, and detailed system scheme is illustrated. Corresponding test results are given to verify the validity of whole system.