System level analysis of a coprocessor architecture for block matching motion estimation computation

被引：0

作者：

Cheung, TKY

Hellestrand, G

Kanthamanon, P

机构：

来源：

ISCAS '97 - PROCEEDINGS OF 1997 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I - IV: CIRCUITS AND SYSTEMS IN THE INFORMATION AGE | 1997年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper describes the design and analysis of a coprocessor architecture for block matching motion estimation algorithm. We have established a system level performance model in terms of various design metrics to estimate the performance cost and to determine a feasible hardware/software partition that satisfies the real-time requirement of the applications.

引用

页码：1580 / 1583

页数：4

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