A high performance lattice architecture of 2D discrete wavelet transform for hierarchical image compression

被引：0
|
作者：
Park, T [1 ]
Jung, SY [1 ]
机构：
[1] Catholic Univ Korea, Bucheon, South Korea
来源：
2002 INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS, DIGEST OF TECHNICAL PAPERS | 2002年
关键词：
D O I：
10.1109/ICCE.2002.1014062
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents high performance lattice architecture of 2D Discrete Wavelet Transform (DWT), which is scalable to extend to an arbitrary 2D DWT with M taps and J levels. The proposed lattice structure fits in a VLSI implementation due to its regularity and shows the period of N-2/2 to compute an NXN image because the even and odd rows are processed simultaneously.
引用
收藏
页码：352 / 353
页数：2
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