Ternary Functions Design Using Memristive Threshold Logic

被引：32

作者：

Soliman, Nancy ^{[1
]}

Fouda, Mohammed E. ^{[2
,3
]}

Alharbi, Abdullah G. ^{[4
]}

Said, Lobna A. ^{[1
]}

Madian, Ahmed H. ^{[1
,5
]}

Radwan, Ahmed G. ^{[2
,6
]}

机构：

[1] Nile Univ, Nanoelect Integrated Syst Ctr, Cairo 12588, Egypt

[2] Cairo Univ, Fac Engn, Engn Math & Phys Dept, Giza 12613, Egypt

[3] Univ Calif Irvine, Elect Engn & Comp Sci Dept, Irvine, CA 92697 USA

[4] Jouf Univ, Fac Engn, Dept Elect Engn, Sakaka 72388, Saudi Arabia

[5] Egyptian Atom Energy Author, Radiat Engn Dept, NCRRT, 29 SOS, Cairo, Egypt

[6] Nile Univ, Sch Engn & Appl Sci, Cairo 12588, Egypt

来源：

IEEE ACCESS | 2019年 / 7卷

关键词：

Ternary numbers; threshold logic; mermistor; VTEAM; CNTFET; STI; PTI; NTI; SBI; STB; SBB; MTL; TLG;

D O I：

10.1109/ACCESS.2019.2909500

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

Memristive threshold logic (MTL) concept is emerged in many circuits to enable high-performance systems in terms of power, energy, area, and delay. This paper proposes a systematic method for building two-bit ternary number functions based on the MTL concept. The proposed method is applied to build the basic ternary arithmetic operations. The implementation of two-bit adder and multiplier is presented in the unbalanced ternary number representation. The proposed designs are verified by using VTEAM memristor and Stanford CNTFET transistor models. Finally, a comparison between the proposed circuits and related work presented in this paper is discussed. It shows that the area in case of the ternary adder is reduced by 30% and 76% and in case of the ternary multiplier by considering that memristors can be stacked above the transistors. In addition, this reduction in the number of transistors reduces the circuit static power and hence improving the overall ternary circuits performance.

引用

页码：48371 / 48381

页数：11