Design of Gate Driver Using Monte Carlo Simulation for Mobility Variation in Organic Thin-Film Transistors

The variation of the propagation delay of each logic circuit causes malfunctioning of the shift register, comprising sequential logic circuits. Thus, it is necessary to know the tolerance of the variations in which normal operation is possible. In this paper, the model for the LTspice using the measured data of an organic thin-film transistor (OTFT) is proposed. Also, we found the conditions under which normal operation was possible by the Monte Carlo simulation with mobility variation added to the proposed OTFT model. An OTFT comprising a bottom-gate/bottom-contact configuration was formed by the drop casting method using the p-type organic semiconductor. The parameter extraction from the experimental data was performed using the least squares method for the OTFT modeling of circuit simulation. The pseudo complementary metal oxide semiconductor logic gates were designed using the OTFT model such as the inverter, NAND, D-flipflop, and 4-bit shift register for the gate driver of the flexible organic light-emitting diode display. The designed logic gates were simulated using the LTspice. V-DD, V-SS, and clock were 10 V, -10 V and 0-10 V 1 kHz, respectively. Normal operation of the 4-bit shift register was confirmed by simulation results on the 1 kHz clock. Also, using the Monte Carlo method which simulated mobility values of 184 OTFTs at random considering the influence of mobility variation in OTFT, it was found that normal operation was possible when the range of mobility variation was within +/- 11%.