A 0.8V CMOS analog decoder for an (8,4,4) extended hamming code

被引：0
|
作者：
Nguyen, N [1 ]
Winstead, C [1 ]
Gaudet, VC [1 ]
Schlegel, C [1 ]
机构：
[1] Univ Alberta, Dept Elect & Comp Engn, Edmonton, AB T6G 2V4, Canada
来源：
2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 1, PROCEEDINGS | 2004年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A novel soft decoding method for iterative error control codes is through the use of analog circuits. Analog decoders exploit the non-linear behaviour of transistors operating in subtheshold to process probability information. This paper describes the design of an (8,4,4) extended Hamming decoder operating at supply voltage 0.8V using 0.18mum CMOS technology. When normalizers are biased at 1 muA, a decoding rate of 444 kbps and energy per decoded bit of 0.64 nJ/b is achieved.
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收藏
页码：1116 / 1119
页数：4
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