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- [41] Development and Investigation of Ultra-Thin Buffer Layers Used in Symmetric Cu/Sn Bonding and Asymmetric Cu/Sn-Cu Bonding for Advanced 3D Integration Applications 2017 12TH INTERNATIONAL MICROSYSTEMS, PACKAGING, ASSEMBLY AND CIRCUITS TECHNOLOGY CONFERENCE (IMPACT), 2017, : 85 - 88
- [42] Low Temperature, Low Pressure CMOS Compatible Cu-Cu Thermo-compression Bonding with Ti Passivation For 3D IC Integration 2015 IEEE 65TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2015, : 2205 - 2210
- [43] Low Temperature (<180°C) Wafer-level and Chip-level In-to-Cu and Cu-to-Cu Bonding for 3D Integration 2013 IEEE 63RD ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2013, : 1146 - 1152
- [45] Room Temperature Desorption of Self Assembly Monolayer (SAM) Passivated Cu for Lowering the Process Temperature Cu-Cu bonding of 3-D ICs 2012 INTERNATIONAL CONFERENCE ON EMERGING ELECTRONICS (ICEE), 2012,
- [46] Low Temperature CMOS Compatible Cu-Cu thermo-compression bonding with constantan alloy passivation for 3D IC Integration 2016 IEEE INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC), 2016,
- [47] Fine-Pitch Interconnection by Hybrid Cu/Sn-Adhesive Bonding for 3D Integration 2014 4TH IEEE INTERNATIONAL WORKSHOP ON LOW TEMPERATURE BONDING FOR 3D INTEGRATION (LTB-3D), 2014, : 48 - 48
- [48] Fine-pitch interconnection by hybrid Cu/Sn-adhesive bonding for 3D integration (1) Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169-8555, Japan; (2) Toray Engineering, 1-45, Oe 1-chome, Otsu, Shiga 520-2141, Japan; (3) Toray Industries Inc., Electronic and Imaging Materials Res. Labs., 3-1-2 Sonoyama, Otsu, Shiga 520-0842, Japan; (4) National Institute for Material Science, 1-1 Namiki, Tsukuba, Ibaraki 305-0044, Japan, 1600, Technology Society; The IEEE Components, Packaging, and Manufacturing (IEEE Computer Society):