A Modified PWM Technique to Improve Total Harmonic Distortion of Multilevel Inverter

被引:0
作者
Podder, Shuvankar [1 ]
Biswas, Md Multan [2 ]
Khan, Md. Ziaur Rahman [1 ]
机构
[1] Bangladesh Univ Engn & Technol, Dept Elect & Elect Engn, Dhaka 1205, Bangladesh
[2] Univ South Carolina, Dept Elect Engn, Columbia, SC 29208 USA
来源
2016 9TH INTERNATIONAL CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING (ICECE) | 2016年
关键词
PWM; Multilevel inverter; THD; MODULATION TECHNIQUES; CONVERTER;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this study, a modified carrier is proposed to generate PWM gating signal. Proposed PWM method reduces total harmonic distortion (THD) of the output voltage of inverter up to 5.8% than the traditional triangular carrier based PWM. Major harmonic components in output voltage are less in magnitude when proposed PWM technique is applied to inverter. Fundamental component of output voltage is also higher in proposed PWM method for all modulation index and frequency ratio. Performance of proposed modified carrier based PWM is evaluated by MA TLAB simulation for single phase 4-cells 9-levels cascaded H-bridge MLI.
引用
收藏
页码:515 / 518
页数:4
相关论文
共 13 条
[1]  
[Anonymous], 2003, IEEE SERIES POWER EN
[2]   A New General Topology for Cascaded Multilevel Inverters With Reduced Number of Components Based on Developed H-Bridge [J].
Babaei, Ebrahim ;
Alilu, Somayeh ;
Laali, Sara .
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, 2014, 61 (08) :3932-3939
[3]   A Cascade Multilevel Converter Topology With Reduced Number of Switches [J].
Babaei, Ebrahim .
IEEE TRANSACTIONS ON POWER ELECTRONICS, 2008, 23 (06) :2657-2664
[4]   A boost DC-AC converter: Analysis, design, and experimentation [J].
Caceres, RO ;
Barbi, I .
IEEE TRANSACTIONS ON POWER ELECTRONICS, 1999, 14 (01) :134-141
[5]   Studying the effect of over-modulation on the output voltage of three-phase single-stage grid-connected boost inverter [J].
Elserougi, A. Abbas ;
Abdel-Khalik, A. S. ;
Massoud, A. ;
Ahmed, S. .
ALEXANDRIA ENGINEERING JOURNAL, 2013, 52 (03) :347-358
[6]  
Liu F, POW EL MOT CONTR C 2
[7]  
McGrath BP, 2002, IEEE T IND ELECTRON, V49, P858, DOI [10.1109/TIE.2002.801073, 10.1109/TIE.2002.801073.]
[8]   Space vector based hybrid PWM techniques for reduced current ripple [J].
Narayanan, G. ;
Zhao, Di ;
Krishnamurthy, Harish K. ;
Ayyanar, Rajapandian ;
Ranganathan, V. T. .
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, 2008, 55 (04) :1614-1627
[9]   Analysis of THD and output voltage performance for cascaded multilevel inverter using carrier pulse width modulation techniques [J].
Palanivel, P. ;
Dash, S. S. .
IET POWER ELECTRONICS, 2011, 4 (08) :951-958
[10]  
Renzhong X., 2013, INT J COMPUTER ELECT, V5