Hardware implementation of evolutionary algorithms using dynamic reconfiguration technology

被引：1

作者：

Kanasugi, Akinori ^{[1
]}

Tsukahara, Akihiko ^{[1
]}

Ando, Ki ^{[1
]}

机构：

[1] Tokyo Denki Univ, Dept Elect & Elect Engn, Adachi Ku, Tokyo 1208551, Japan

来源：

NATURAL COMPUTING | 2015年 / 14卷 / 04期

关键词：

Evolutionary algorithm; Dynamic reconfiguration; FPGA;

D O I：

10.1007/s11047-014-9476-z

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper proposes hardware implementation of evolutionary algorithms using dynamic reconfiguration technology. In this paper two types of dynamic reconfiguration for evolutionary algorithm are introduced. The processor was designed by using VHDL and the circuit was simulated. The effectiveness of the proposal processor was confirmed.

引用

页码：593 / 601

页数：9

共 7 条

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[2]

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[3]

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[5]

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[6]

TANESE R, 1989, PROCEEDINGS OF THE THIRD INTERNATIONAL CONFERENCE ON GENETIC ALGORITHMS, P434

[7]

Tsukahara A, 2009, INT J CONTROL AUTOM, V7, P1, DOI [10.1007/s12555-009-0101-3, 10.1007/S12555-009-0101-3]

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