Physical modeling of negative bias temperature instabilities for predictive extrapolation

被引：20

作者：

Huard, V. ^{[1
]}

Parthasarathy, C. R. ^{[2
]}

Guerin, C. ^{[2
]}

Denais, M. ^{[2
]}

机构：

[1] Philips Semicond, 850 Rue Jean Monnet, F-38926 Crolles, France

[2] ST MicroelectCrolles2 Alliance, F-38926 Crolles, France

来源：

2006 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 44TH ANNUAL | 2006年

关键词：

D O I：

10.1109/RELPHY.2006.251348

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Based on new insights on measurement methodologies, inter-face traps creation and hole trapping as root causes of NBTI degradation are investigated in this paper. Physical modeling is proposed and the related extrapolation laws are discussed.

引用

页码：733 / +

页数：2

共 4 条

[1]

DENAIS M, 2004, P IEDM

[2] High-performance chip reliability from short-time-tests - Statistical models for optical interconnect and HCI/TDDB/NBTI deep-submicron transistor failures [J].

Haggag, A ;

McMahon, W ;

Hess, K ;

Cheng, K ;

Lee, J ;

Lyding, J .

39TH ANNUAL PROCEEDINGS: INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM 2001, 2001, :271-279

[3] EFFECTS OF OXIDE TRAPS ON MOS CAPACITANCE [J].

HEIMAN, FP ;

WARFIELD, G .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1965, ED12 (04) :167-&

[4]

YANG T, 2005, P S VLSI TECHN

← 1 →