10 Gbit/s 0.0065 mm2 6 mW analogue adaptive equaliser utilising negative capacitance

被引：19

作者：

Lee, D. ^{[1
]}

Han, J. ^{[1
]}

Han, G. ^{[2
]}

Park, S. M. ^{[2
]}

机构：

[1] Yonsei Univ, Dept Elect & Elect Engn, Seoul 120749, South Korea

[2] Ewha Womans Univ, Dept Elect Engn, Seoul, South Korea

来源：

ELECTRONICS LETTERS | 2009年 / 45卷 / 17期

关键词：

D O I：

10.1049/el.2009.1525

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An area- and power-efficient analogue adaptive equaliser (AEQ) is realised in a 0.13 mu m CMOS technology. The negative capacitance circuits are exploited at the equalisation filter to achieve wider bandwidth and larger high-frequency boosting, instead of using passive inductors that lead to a large chip area. Measured results demonstrate the data rate of 10 Gbit/s for 20 and 34 inch FR4 traces as channels, while dissipating only 6 mW from a single 1.2 V supply. The chip core occupies an extremely small area of 50 x 130 mu m(2). To the best of the authors' knowledge, this chip achieves the lowest power consumption and the smallest chip area among the recently reported AEQs.

引用

页码：863 / 864

页数：2