Silicon Etch with Integrated Metrology for Through Silicon Via (TSV) Reveal

被引：0
|
作者：
Mauer, Laura B. [1 ]
Taddei, John [1 ]
Lawrence, Elena [1 ]
Youssef, Ramey [1 ]
Olson, Stephen P. [2 ]
机构：
[1] Solid State Equipment LLC, Horsham, PA 19044 USA
[2] SEMATECH, Albany, NY 12203 USA
来源：
2013 IEEE INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC) | 2013年
关键词：
TSV; endpoint detection; TTV; reveal height; wet etch;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Wet etch is a cost-effective process option to reveal through-silicon vias (TSVs). This paper addresses the methodology for using integrated wafer thickness measurements to provide complete process control.
引用
收藏
页数：4
相关论文
共 50 条
  • [21] Metrology needs for through-silicon via fabrication
    Vartanian, Victor
    Allen, Richard A.
    Smith, Larry
    Hummler, Klaus
    Olson, Steve
    Sapp, Brian
    JOURNAL OF MICRO-NANOLITHOGRAPHY MEMS AND MOEMS, 2014, 13 (01):
  • [22] High Speed Copper Electrodeposition for Through Silicon Via(TSV)
    Kondo, Kazuo
    Suzuki, Yushi
    Saito, Takeyasu
    Okamoto, Naoki
    PROCESSING, MATERIALS, AND INTEGRATION OF DAMASCENE AND 3D INTERCONNECTS, 2010, 25 (38): : 127 - 131
  • [23] Modeling and Analysis of Cracked Through Silicon Via (TSV) Interconnections
    Gerakis, Vasileios
    Avdikou, Christina
    Liolios, Alexandros
    Hatzopoulos, Alkis
    PROCEEDINGS OF THE 2014 IEEE 17TH INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS & SYSTEMS (DDECS), 2014, : 310 - 313
  • [24] Through Silicon Via (TSV) Defect Modeling, Measurement, and Analysis
    Jung, Daniel H.
    Kim, Youngwoo
    Kim, Jonghoon J.
    Kim, Heegon
    Choi, Sumin
    Song, Yoon-Ho
    Bae, Hyun-Cheol
    Choi, Kwang-Seong
    Piersanti, Stefano
    de Paulis, Francesco
    Orlandi, Antonio
    Kim, Joungho
    IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2017, 7 (01): : 138 - 152
  • [25] Front End of Line Through Silicon Via (TSV) Integration
    Shinde, Subhash L.
    Bauer, Todd M.
    Massad, Jordan A.
    Hetherington, Dale
    MATERIALS AND TECHNOLOGIES FOR 3-D INTEGRATION, 2009, 1112 : 151 - 157
  • [26] Volcano effect in open through silicon via (TSV) technology
    Kraft, J.
    Stueckler, E.
    Cassidy, C.
    Niko, W.
    Schrank, F.
    Wachmann, E.
    Gspan, C.
    Hofer, F.
    2012 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2012,
  • [27] A novel guard method of through-silicon-via (TSV)
    Wang, Fengjuan
    Huang, Jia
    Yu, Ningmei
    IEICE ELECTRONICS EXPRESS, 2018, 15 (11):
  • [28] Optimization of Cu Electrodeposition Parameters for Through Silicon Via (TSV)
    Noh, Sang-Soo
    Choi, Eun-Hey
    Lee, Yong-Hyuk
    Ju, Hyun-jin
    Rha, Sa-Kyun
    Lee, Boung-ju
    Kim, Dong-Kyu
    Lee, Youn-Seoung
    2011 18TH IEEE INTERNATIONAL SYMPOSIUM ON THE PHYSICAL AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS (IPFA), 2011,
  • [29] High Speed Copper Electrodeposition for Through Silicon Via(TSV)
    Hayashi, Taro
    Kondo, Kazuo
    Takeuchi, Minoru
    Suzuki, Yushi
    Saito, Takeyasu
    Okamoto, Naoki
    Marunaka, Masao
    Tsuchiya, Takayuki
    Bunya, Masaru
    PROCESSING MATERIALS OF 3D INTERCONNECTS, DAMASCENE AND ELECTRONICS PACKAGING, 2012, 41 (43): : 45 - 51
  • [30] Active Circuit to Through Silicon Via (TSV) Noise Coupling
    Cho, Jonghyun
    Shim, Jongjoo
    Song, Eakhwan
    Pak, Jun So
    Lee, Junho
    Lee, Hyungdong
    Park, Kunwoo
    Kim, Joungho
    ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS, 2009, : 97 - +
12345