Silicon Etch with Integrated Metrology for Through Silicon Via (TSV) Reveal

被引：0
|
作者：
Mauer, Laura B. [1 ]
Taddei, John [1 ]
Lawrence, Elena [1 ]
Youssef, Ramey [1 ]
Olson, Stephen P. [2 ]
机构：
[1] Solid State Equipment LLC, Horsham, PA 19044 USA
[2] SEMATECH, Albany, NY 12203 USA
来源：
2013 IEEE INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC) | 2013年
关键词：
TSV; endpoint detection; TTV; reveal height; wet etch;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Wet etch is a cost-effective process option to reveal through-silicon vias (TSVs). This paper addresses the methodology for using integrated wafer thickness measurements to provide complete process control.
引用
收藏
页数：4
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