An Encoder/Decoder with Throughput over Gigabits/sec for Rate-compatible LDPC Codes with Wide Code Rates

A challenge in the design of rate-compatible (RC) low-density parity-check (LDPC) codes is how to maximize the range of code rates. In this paper, we propose a class of RC LDPC codes with a very wide range of code rates. To ensure linear encoding, dual-diagonal form for the parity part of the mother parity-check matrix is used. Constructed from shifted identity matrices, the proposed codes are particularly well-suited for the high-speed implementation of parallel encoders and parallel decoders. To widen the range of code rates, we have proposed an optimal transmission scheme, which keeps the optimal degree distribution unchanged for the mother code and all daughter codes. Thus, the proposed technique pushes the upper bound of code rates to 0.96, which is the highest rate in RC LDPC codes in the world, based on our best knowledge. The implementation results into field programmable gate array (FPGA) devices indicate that a parallel encoder (decoder) for the proposed RC LDPC codes is capable of reaching a throughput of 7.2 (1.8) Gigabits per second using a clock frequency of 150 MHz.