A Wideband 400 MHz-to-4 GHz Direct RF-to-Digital Multimode ΔΣ Receiver

被引：31
|
作者：
Wu, Charles [1 ]
Alon, Elad [1 ]
Nikolic, Borivoje [1 ]
机构：
[1] Berkeley Wireless Res Ctr, Berkeley, CA 94704 USA
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2014年 / 49卷 / 07期
关键词：
ADC; bandpass ADC; CMOS; Delta Sigma ADC; LNTA; receiver; software-defined radio; MODULATOR; JITTER; DB; CLOCK; ADC; MHZ;
D O I：
10.1109/JSSC.2014.2319249
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A wide-tuning-range low-power sigma-delta-based direct-RF-to-digital receiver architecture is implemented in 65 nm CMOS. A flat signal transfer function is chosen to support wide-frequency-range radios. A multilevel (two-bit) nonreturn-to-zero DAC improves jitter immunity to enable a high dynamic range, and, with a class-AB low-noise transconductance amplifier, guarantees a highly linear front end. For a 4 MHz signal, the peak SNDR of the receiver exceeds 68 dB and is better than 60 dB across the 400 MHz to 4 GHz carrier frequency range. By virtue of utilizing a negative feedback digitizer close to the antenna, an IIP3 of 10 dBm is achieved while dissipating only 40 mW from 1.1 V/1.5 V supply voltages.
引用
收藏
页码：1639 / 1652
页数：14
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